1. Field of the Invention
The present invention relates to technology for heightening the operating speed of a semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor integrated circuits have steadily heightened their operating speed owing to the progress of semiconductor manufacturing technology. In particular, the operating frequency of a logic LSI such as microcomputer has been yearly enhanced, and the difference thereof from the operating frequency of a memory LSI such as DRAM has been expanding.
In order to reduce such difference, there have been developed high-speed DRAMs of clock synchronous type such as SDRAM (Synchronous DRAM), RDRAM (Rambus DRAM) and SLDRAM (SyncLink DRAM).
The high-speed DRAM of this type is possible to read and write the data of sequential addresses at high speed by an input/output circuit operating in synchronization with a clock signal, and an extended internal bus. Therefore, the high-speed DRAMs are often employed for the main storages of personal computers and workstations.
Meanwhile, in the high-speed DRAM of this type, the operating speed of a memory core is almost the same as that of a conventional DRAM. Consequently, the data transfer of (random access to) not sequential addresses is not much faster as compared with the data transfer of the sequential addresses.
As a result, it is sometimes difficult to adopt the high-speed DRAM due to a low data transfer rate in a field such as image processing, where the random access occurs frequently.
However, a DRAM capable of random access at high speed has been demanded even in such field since the DRAM is less expensive than an SRAM.